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PIC18C601/801
DS39541A-page 308
Advance Information
2001 Microchip Technology Inc.
C
CALL ................................................................................ 230
Capture (CCP Module) .................................................... 142
Block Diagram ......................................................... 143
CCP Pin Configuration ............................................. 142
CCPR1H:CCPR1L Registers ................................... 142
Changing Between Capture Prescalers ................... 143
Software Interrupt .................................................... 143
Timer1 Mode Selection ............................................ 142
Capture/Compare/PWM (CCP) ....................................... 141
Capture Mode. See Capture
CCP1 ....................................................................... 142
CCPR1H Register ........................................... 142
CCPR1L Register ............................................ 142
CCP2 ....................................................................... 142
CCPR2H Register ........................................... 142
CCPR2L Register ............................................ 142
Compare Mode. See Compare
Interaction of Two CCP Modules ............................. 142
PWM Mode. See PWM
Registers Associated with Capture
and Compare ........................................... 145
Timer Resources ..................................................... 142
Timing Diagram ....................................................... 282
Chip Select
Chip Select 2 (CS2) ................................................... 71
Chip Select I/O (CSIO) ...................................................... 71
Chip Selects
Chip Select 1 (CS1) ................................................... 71
Clocking Scheme ............................................................... 46
CLRF ............................................................................... 231
CLRWDT ......................................................................... 231
Code Examples ............................................................... 154
Changing Between Capture Prescalers ................... 143
Clearing RAM Using Indirect Addressing .................. 59
Combination Unlock (Macro) ..................................... 51
Combination Unlock (Subroutine) .............................. 50
Fast Register Stack ................................................... 45
Initializing PORTA .................................................... 103
Initializing PORTB .................................................... 105
Initializing PORTC ................................................... 108
Initializing PORTD ................................................... 110
Initializing PORTE .................................................... 113
Initializing PORTF .................................................... 116
Initializing PORTG ................................................... 119
Initializing PORTH ................................................... 121
Initializing PORTJ .................................................... 124
Programming Chip Select Signals ........................... 116
Saving STATUS, WREG and BSR Registers .......... 101
Table Read ................................................................ 75
Table Write ................................................................ 77
COMF .............................................................................. 232
Compare (CCP Module) .................................................. 144
Block Diagram ......................................................... 144
CCP Pin Configuration ............................................. 144
CCPR1H:CCPR1L Registers ................................... 144
Software Interrupt .................................................... 144
Special Event Trigger .................... 133
, 139, 144, 200
Timer1 Mode Selection ............................................ 144
Configuration Address Map, Example ............................... 71
Configuration Bits ............................................................ 207
Table ........................................................................ 207
Context Saving During Interrupts ..................................... 101
CPFSEQ .......................................................................... 232
CPFSGT .......................................................................... 233
CPFSLT ........................................................................... 233
D
Data Memory ..................................................................... 49
General Purpose Registers ....................................... 49
Special Function Registers ........................................ 49
Data Memory Map
Program Bit Not Set .................................................. 51
Program Bit Set ......................................................... 52
DAW ................................................................................ 234
DC and AC Characteristics Graphs and Tables .............. 295
DCFSNZ .......................................................................... 235
DECF ............................................................................... 234
DECFSZ .......................................................................... 235
Development Support ...................................................... 259
Development Tool Version Requirements ....................... 305
Device Differences .......................................................... 303
Device Migrations ............................................................ 304
Direct Addressing .............................................................. 60
E
Electrical Characteristics ................................................. 265
Errata ................................................................................... 7
External Wait Cycles ......................................................... 72
F
Fast Register Stack ........................................................... 45
Firmware Instructions ...................................................... 215
G
General Call Address Sequence ..................................... 162
General Call Address Support ......................................... 162
GOTO .............................................................................. 236
I
I/O Mode .......................................................................... 119
I/O Ports .......................................................................... 103
I2C (SSP Module) ............................................................ 159
ACK Pulse .......................................................159
, 160
Addressing .............................................................. 160
Block Diagram ......................................................... 159
Read/Write Bit Information (R/W Bit) ....................... 160
Reception ................................................................ 160
Serial Clock (RC3/SCK/SCL) .................................. 160
Slave Mode ............................................................. 159
Timing Diagram, Data ............................................. 287
Timing Diagram, START/STOP Bits ....................... 287
Transmission ........................................................... 160
I2C Master Mode Reception ............................................ 167
I2C Master Mode RESTART Condition ........................... 166
I2C Module
Acknowledge Sequence Timing .............................. 170
Baud Rate Generator .............................................. 164
Block Diagram ................................................. 164
BRG Reset due to SDA Collision ............................ 174
BRG Timing ............................................................. 165
Bus Collision
Acknowledge ................................................... 172
RESTART Condition ....................................... 175
RESTART Condition Timing (Case1) .............. 175
RESTART Condition Timing (Case2) .............. 175
START Condition ............................................ 173
START Condition Timing ........................173
, 174
STOP Condition .............................................. 176
STOP Condition Timing (Case1) ..................... 176
STOP Condition Timing (Case2) ..................... 176
Transmit Timing .............................................. 172
Bus Collision Timing ................................................ 172
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